Design of the Lower Error Fixed-Width Multiplier and Its Application
نویسندگان
چکیده
This brief develops a general methodology for designing a lower-error two’s-complement fixed-width multiplier that receives two -bit numbers and produces an -bit product. By properly choosing the generalized index, we derive the better error-compensation bias to reduce the truncation error and then construct a lower error fixed-width multiplier, which is area efficient for VLSI implementation. Finally, we successfully apply the proposed fixed-width multiplier to realizing a digital FIR filter, which has shown that the performance is better than that using other fixed-width multipliers.
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